1. Field of the Invention
This invention relates generally to non-volatile memories, and, more specifically, to methods for treating over-erased memory cells in electrically erasable and programmable read only memories (EEPROMs).
2. Background Information
A non-volatile memory (NVM) cell stores information by altering the control-gate voltage required to enable source-drain current conduction. This is known as the cell""s threshold voltage, Vt. Programming is the operation used to raise this conduction threshold, while erase is an operation used to lower the cell""s threshold. A virtual-ground architecture is one of a few schemes used to assemble NVM cells into arrays. A virtual-ground array offers relatively high area efficiency by allowing the adjacent cell to share access bit-lines.
A schematic of a virtual-ground array 100 is illustrated in FIG. 1a, with the various parts of an individual cell 120 also described in FIG. 1b. Here, vertical bit-lines connect NVM cell source and drain terminals, 123 and 124, while horizontal word-lines connect to the terminals of the control gate 121. The program status of a specific cell within the array is isolated for reading by applying the appropriate bit-line and word-line bias voltages. In FIG. 1, cell xcex12 102 is read when word-line WL0 130 and bit-line BLxcex11 111 are biased high while bit-line BLxcex12 112 and word-line WL1 131 are set low. Alternatively, cell xcex11 is read when BLxcex10 110 is set low instead of BLxcex12 112. This array architecture derives its name from this use of ground bias in selecting individual cells instead of having dedicated source bit-lines. Further details on the virtual-ground architecture are given in J. Pasternak, et. al., xe2x80x9c4 Mb Alternate Metal, Virtual Ground FLASH Memory,xe2x80x9d 1998 NVSM Workshop, Monterey, Calif. (USA), which is hereby incorporated by this reference, and also in the other reference incorporated below.
An important consideration for virtual-ground operation is the influence of neighboring cells on the selected cell. Neighbor cells can draw current away from the cell being accessed; an unwanted situation since it interferes with the accuracy and efficiency of both read and program operations. This neighbor effect is typically reduced by biasing neighboring bit-lines to the same levels as those accessing the cell, as illustrated in FIG. 2. Here, a current 201 is flowing in cell xcex12, for example during reading or programming, by setting the drain, connected to BLxcex11 211, and control gate, connected to word-line WL0 230, both high, while the source, connected to bit line BLxcex12 212, and other word-lines are low. A current in the neighboring cells xcex11 and xcex13, respectively due to the drain-neighbor leakage 202 or source-neighbor leakage 203, may also be induced unless these cells are biased properly with a high drain neighboring bit-line BLxcex10 210 and the low source neighboring bit-line BLxcex13 213.
By definition, FLASH-cell erasure requires the erase of at least an entire sector, which is usually a word-line, of cells. Due to differences in erase rates of the various cells on this common word-line, cells may often erase beyond the maximum lower threshold voltage needed to reliably indicate an erased state. As a result, neighbor effects are significantly enhanced for these over-erased cells. Soft programming is a technique used to gently raise the thresholds of over-erased cells prior to the actual data programming.
Prior art methods for treating over-erased cells include individually programming the over-erased cells until they are in the erased, or xe2x80x9cgroundxe2x80x9d state. More details on some of these techniques can be found in U.S. Pat. Nos. 5,172,338 and 5,272,669, both of which are assigned to SanDisk Corporation and both of which are hereby incorporated herein by this reference.
Source-side injection is one of the many mechanisms that can be used to program an NVM cell. FIG. 3a shows a device cross-section of a structure for programming by source-side injection, with its schematic symbol shown in FIG. 3b. The cell 300 shown in these figures has a source 303 and drain 305 that define the channel region between them, over which is the control gate 309 and the floating gate 307 as well as the side-wall 301. This structure generally requires a low-conductive channel region 311 near the source side of the device, and a highly conductive, floating-gate channel region 313. In this device, the lateral field along the channel is enhanced at the floating gate""s source side through the combination of the side-wall and floating-gate channel regions. The sidewall device 301 is biased through coupling from the relatively high control gate voltage needed for programming. More detail on source-side injection is given, for example, in A. T. Wu, T. Y. Chan, P. K. Ko, C. Hu, xe2x80x9cA Novel High-Speed, 5-Volt Programming EPROM Structure with Source-Side Injection,xe2x80x9d 1986 IEDM Technical Digest, pp. 584-587, which is hereby incorporated herein by this reference.
In order to limit the total soft-program current and also control the soft-program rate, the cell""s programming current can be controlled from the source-side when using source-side injection. A complication to this approach for virtual-ground arrays is the source-neighbor effect due to over-erased cells. FIG. 4 shows a program current applied to cell xcex12 using a source-limit circuit in a virtual ground array of cells like those of FIG. 3a in the situation where neighboring cell xcex13 is over-erased. To program cell xcex12, the current 401 is set up by setting bit-line BLxcex11 411 and word-line WL0 420 high. The other word-lines, such as WL1 421, are set low. The program current 401 is then controlled by the current limiter 431 on the source bit-line BLxcex12 412. Although the bit-line BLxcex12 412 is connected to ground below 431, the voltage level at node A is some non-zero value that is dependent on the characteristics of the cell xcex12 and is very dynamic. Since the source neighbor bit-line BLxcex13 413 is at ground and the word-line WL0 420 is high, instead of the programming current flowing solely through the current-limit circuit 431, an uncontrolled source-neighbor leakage current 403 runs through cell xcex13 and out through source-neighbor bit line BLxcex13 413.
This resultant uncontrolled current through cell xcex13 results in a number of problems. A first problem is power consumption. This xcex13 sort of leakage is an uncontrolled flow of current. As a large number of cells are generally programmed in parallel, this results in greatly increased power consumption, which is a particular problem in low power applications. A second problem is that since the amount of current 403 flowing in cell xcex13 cannot be controlled, the current 401 in the cell to be programmed can not be controlled accurately. The more current flowing through xcex12, the faster it will program. Thus, by not being able to control the current accurately, a greater variation in the program rates of the cells being programmed results. Additionally, if the cell xcex12 is over-erased, it will draw more current, further compounding the programming rate problem.
Therefore, a solution to this problem of improving the control of the soft-programming current in a virtual ground arrays is needed.
The present invention is directed to controlling programming current in a virtual-ground array memory architecture. The invention consists of circuitry to bias the array such that no source neighbors occur during soft programming. A feature of this bias configuration is that two cells are simultaneously soft-programmed. This dual-cell operation relies on the fact that neighbor cells will have similar electrical characteristics and will therefore program at a similar rate.
In one exemplary embodiment, the cells of the non-volatile memory array are programmed by a source side injection mechanism. Adjacent cells along a word-line share a common source line and are programmed together until one of the cells is verified to have the desired threshold value. The number of bit-lines between source lines can be as few as one, the actual drain required for programming. An additional means for controlling the soft-program rate is realized through the choice of the word-line voltage applied.
Another exemplary embodiment uses memory cells with multiple floating gates. In this embodiment, the floating gate transistors within a cell are soft programmed separately from each other, but as part of a pair formed with a floating gate transistor in an adjacent cell.
In any of the embodiments, more than one such pair, each from a separate block, may be soft-programmed simultaneously. The process can continue until either a first of these pairs, or until all of these pairs, no longer have both members of the pair over-erased.
Additional aspects, features and advantages of the present invention are included in the following description of specific representative embodiments, which description should be taken in conjunction with the accompanying drawings.